NRAM....how nram helps in logic folding and reconfiguration

Then how the reconfiguration is performed? The figure shows the detail structure of NRAM. Each cell contains one bit and can be separately addressed by the word line and bit line. Whether the cell stores a 1 or 0 determines the high or low voltage at the output. Only during initialization, the reconfiguration bits will be written into the cells. Then during run-time reconfiguration, a reconfiguration copy will be read out from NRAM cells and put into the SRAMs to support the current computation or connectivity. Then let’s look at the reconfiguration overhead. First, the reconfiguration time is short, only around 160ps. That means there is almost no delay overhead. Then consider about the area overhead, assume there are 16 reconfiguration sets in the NRAM and we use 100nm technology for CMOS logic and 100nm nanotube length, through Layout the LB including the periphery interconnect, the area overhead is around 20.5% per LB. However, the logic density improves nearly k-fold. Here logic density is defined as, give an amount of area, if there are 16 reconfiguration copies. It can implement 16 times more logic than the original. Then counting the area overhead, logic density is the logic the effective area can implement. We can see that with a relative low overhead, we can gain large logic density improvement. The capacity of NRAM, parameter k, is very important. Too large k will waste area and too small k will affect performance. The optimal k value can be obtained through design space exploration. .......................

Example--->

Reconfiguration time short: 160ps
Area overhead of NRAMs
k: no. of reconfiguration sets per NRAM, assume k = 16
Area overhead: 20.5% per LB, assuming 100nm technology for CMOS logic and nanotube length
Logic density = k (conf. copies) x area per configuration = 16*(1-0.205)=12.75
Appropriate value for k obtained through design space exploration